The present invention relates to processor-to-processor communication processing in a distributed memory parallel computer system and a communication processing method in the parallel computer for attaining high speed parallel program execution.
JP-A-5-46576 discloses a communication control system in which each of the processor units (hereinafter referred to as PUs) in the parallel computer system assigns a data transmission area on a memory and when data is written on that area, data is transmitted to a predetermined receiving PU identification code and a specified address of the memory.
The above prior art has the following problems.
The data transmitting PU cannot determine whether the destination PU issues a receive request or not because it does not know the status of the data receiving PU.
Accordingly, it is necessary to synchronize the transmitting PU with the receiving PU in the communication processing or secure an area in the receiving PU for temporarily buffering data transmitted from the transmitting PU and copy the data from the buffer area to the memory as required.
When the synchronization is made between the transmitting PU and the receiving PU, an interruption process by an operating system takes place and performance is lowered. In the approach of providing a data buffer area for the transmitting data in the receiving PU, a copy process from the buffer area to the memory is required and the copy time causes an overhead and performance is sacrificed.